Field of Invention
The present invention relates to a chip package and a method of manufacturing the same.
Description of Related Art
With the requirement for small size, light weight, and multiple functions of electronic devices, the semiconductor chips in the electronic devices need a reduced size and an increased wiring density. Therefore, it becomes more difficult and challenging to fabricate a semiconductor chip package in the manufacturing process for the semiconductor chips. Wafer-level chip package is a method for packaging the semiconductor chips, in which after completing the manufacture of all chips on the wafer, these chips are packaged and tested on the wafer, and followed by a cutting process to form a number of individual chip packages.
Since the size of the semiconductor chip is reduced and the wiring density is increased, the usage of epitaxy layers in the chip not only shortens the time of charge collection but further increase the overall efficiency of the chip package. However, it probably occurs an incorrect electrical connection between the conductive epitaxy layer and a conductive layer subsequently formed by a wire-bonding process, thereby unfavorably forming a short circuit in the chip package and decreasing the yield of the chip package. Accordingly, related industry urgently needs an improved chip package structure and manufacturing method to prevent the problem discussed above.